Integrated circuit (IC) technology is continuously increasing in complexity due to improvements in semiconductor process fabrication techniques. Complete system-on-chip (SoC) solutions, involving many elements such as a processor, timer, interrupt controller, bus, memory, and/or embedded software on a single circuit, are now available for a variety of applications. Software development, early hardware architecture exploration and functional verification of a complex SoC circuit or processor device are challenges faced by the semiconductor industry. At process fabrication technologies of 32 nm or smaller (e.g., advanced technology nodes), with millions or more of transistors available to implement large and complex SoC circuits, the challenge of functionally verifying such complex devices grows exponentially. Industry data suggests that upwards of 80% of all project resources are allocated to software development and functional verification of these devices.
An IC design process typically begins with a software program that describes the behavior or functionality of a circuit to be created. Such a software program is typically written in procedural programming languages such as C, C++, Verilog, and VHDL that define behavior to be performed with limited implementation details. The IC design process involves complex sub-processes each requiring one or more intermediate steps. At each of these intermediate steps, the IC design is represented at a different level of specificity.
One of higher level descriptions of an IC design is a register transfer level (RTL) design. In the RTL design, variables and data operators represent the IC components such as registers and functional blocks of the sections of the IC. Being a more generic high-level description of the IC design, the RTL design could be easily mapped across different IC design process technologies.
The next lower level description of the IC design is a gate-level design at which the IC is defined as a set of interconnecting logic gates such as AND, OR gates and memory components such as flip-flops. The IC design at this level of specificity will be referred to as a “netlist” in the following discussion. A netlist is a more specific definition of the IC design in the gate-level design than that in the RTL design. Also, the gate-level design is typically technology and process specific. Thus, it can be understood by people of ordinary skill in the art that verifying/simulating an IC design in the gate-level takes much more resource and time t0 finish than in the RTL. However, lately, there is an increasing trend in industry to perform at least one gate-level simulation before going into a last stage of chip manufacturing since the gate-level simulation typically provides more accurate results, which advantageously increases confidence in verifying the IC design's power, performance, timing, area estimations, etc.